A gate signal of an existing gate drive circuit is output line by line; at present, in an OLED design, an output of the gate signal needs an interlaced output structure. Therefore, in a shifting register controlled by an existing dual clock, there is a suspended state of time sequence between line n and line n+2 (i.e., on a certain time sequence, there is no direct signal input at a level on a key circuit node, then the level on the node is in a suspended state), the output stability of the shifting register thus becomes worse.
As shown in FIG. 1, an existing shifting register structure controlled by a simple three-clock is shown; FIG. 2 shows a GOA clock time sequence for the operation thereof. The working principle of the structure is as follows; the working process of the shifting register can be divided into four parts, which can be seen in the shifting register time sequence shown in FIG. 2.
At a first phase: CLK is a low voltage turn-on signal, transistors M23 and M21 are turned on; after M23 is turned on, the low voltage signal of STV then reaches node B via M23, such that M22 is turned on, now the high voltage turn-off signal of CLKB is output to the output terminal OUT of the shifting register; at the same time the node B also controls the transistor M12, such that a high voltage VGH signal is input to the node C; after the transistor M21 is turned on, a low voltage VGL signal arrives at the node A via M21 to turn on M19; the high voltage VGH signal is also output to the output terminal OUT of the shifting register through the M19.
At a second phase: CLK is turned off; CLKB is a low voltage signal; now the low voltage signal saved in the node B also keeps M22 and M12 in an on-state. M22 is turned on such that a low voltage signal of CLKB is output to the output terminal OUT of the shifting register; M12 is turned on such that VGH is still input to the node C; while M20 controlled by CLKB is turned on, such that the VGH signal of node C is input to the node A; M19 is then in an off-state, without affecting the output terminal OUT.
At a third phase: CLK is a low voltage signal; CLKB is a high voltage signal. The low voltage signal of CLK turns on M23 and M21. After M23 is turned on, STV signal becomes high voltage and arrives at node B via M23, such that M22 and M12 are turned off; while M21 is turned on, such that VGL signal is output to the node A, turning on M19; a high voltage VGH is input to the output terminal OUT of the shifting register.
At a fourth phase: CLKB is a low voltage signal; CLK is a high voltage signal. When CLK is a high voltage signal, M21 is turned off, while CLKB turns on M20, the level of the suspended node C (i.e., the remnant of VGH of the second phase) interferes with the level of the suspended node A (i.e., the remnant of VGL of the third phase), thereby affecting the on-state of M19, and therefore affecting the signal of the output terminal OUT of the shifting register, such that the output signal is unstable.
It can be seen that if the existing shifting register is used for an interlaced output, there is a suspended state of time sequence between line n and line n+2 (i.e., on a certain time sequence, there is no direct signal input at a level on a key circuit node, then the level on the node is in a suspended state), the output stability thus becomes worse.